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Poultry Terminology::
the assignment is scheduled to occur
The first statement in the process assigns the value of w0 to f. This provides a default value for f but the assignment does not actually take place until the end of the process. In VHDL jargon we say that the assignment is scheduled to occur after all of the statements in the process have been evaluated. If another assignment to f takes place while the process is active, the default assignment will be overridden. The second statement in the process assigns the value of w1 to f if the value of s is equal to 1. If this condition is true, then the default assignment is overridden. Thus if s = 0, then f = w0, and if s = 1, then f = w1, which defines the 2-to-1 multiplexer.
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